This invention relates to a method of testing semiconductor chips in multiple stacked configurations with different rotational interconnections and optimizing a stacked chip yield.
Bonding of multiple substrates is required to enable three-dimensional integration of semiconductor chips. Two semiconductor substrates are processed independently, and subsequently brought into physical contact with each other so that one chip in one substrate overlies another chip in another substrate. The functionality of each stacked chip requires functionality of each individual chip within the stacked chip.
Referring to FIG. 1, a commonly encountered situation in manufacturing of stacked semiconductor chips is schematically illustrated. A first wafer has a high yield area, which is herein referred to as a “first wafer high yield area,” and a low yield area, which is herein referred to as a “first wafer low yield area.” Also, second wafer has a high yield area, which is herein referred to as a “second wafer high yield area,” and a low yield area, which is herein referred to as a “second wafer low yield area.”
Because semiconductor chips in each wafer are patterned in the same orientation, the first wafer and the second wafer must be bonded with a unique predetermined azimuthal orientation relative to each other. For example, the requirement for functional bonding between the first and second substrates may be that the notch of the first wafer matches the notch of the second wafer when bonded. In general, once a first wafer and a second wafer to be bonded are determined, there is a one-to-one correspondence between chips on the first substrate and chips on the second substrate. The first and second wafers cannot be expected to produce functional stacked chips if bonded with a relative rotation.
Because the distribution of high yield areas and low yield areas are statistical, the first wafer high yield area may overlie the second wafer low yield area upon bonding, and the first wafer low yield area may overlie the second wafer high yield area upon bonding. In such a case, the yield of the stacked chips is low across the entire bonded structure because the functionality of a stacked chip requires functionality of both an upper chip from the first wafer and a lower chip from the second wafer.